Reference is made to FIG. 1 which shows a schematic diagram of a standard six transistor (6T) static random access memory (SRAM) cell 10. The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel MOSFET transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true data storage node Q and a complement data storage node QB. The cell 10 further includes two transfer (passgate) transistors M5 and M6 whose gate terminals are coupled with a wordline node and are controlled by the signal present at the wordline node (WL). Transistor M5 is source-drain connected between the true data storage node Q and a node associated with a true bitline (BLT). Transistor M6 is source-drain connected between the complement data storage node QB and a node associated with a complement bitline (BLF). The source terminals of the p-channel transistors M2 and M4 in each inverter 12 and 14 are coupled to receive a high supply voltage (for example, Vdd) at a high supply node, while the source terminals of the n-channel transistors M1 and M3 in each inverter 12 and 14 are coupled to receive a low supply voltage (for example, Gnd) at a low supply node. The high supply voltage Vdd at the high supply node and the low supply voltage Gnd at the low supply node comprise the power supply set of voltages for the cell 10.
The gate terminals of the transfer (passgate) transistors M5 and M6 are coupled to a wordline driver circuit 16 through the wordline node WL. The wordline driver circuit 16 is also coupled to receive the high supply voltage (Vdd) at the high supply node.
The true and complement bitlines BLT and BLF are coupled to bitline circuitry 18. The bitline circuitry 18 may comprise, for example, precharge circuitry, sense amplifier circuitry and read/write driver circuitry as known to those skilled in the art. The bitline circuitry 18 is also coupled to receive the high supply voltage (Vdd) at the high supply node.
Reference is now made to FIG. 2 which illustrates a block diagram of a memory device 20 including a plurality of cells 10 like that shown in FIG. 1 arranged in a matrix of rows and columns. The bit lines BLT/BLF of a plurality of cells 10 in a column are coupled together and to the bitline circuitry 18. The wordlines WL of a plurality of cells 10 in a row are coupled together and to the wordline driver circuit 16. The memory device 20 may further include additional circuitry, known to those skilled in the art but not shown in FIG. 2, including address decoder circuitry and input/output circuitry.
With the prior art configuration of FIGS. 1 and 2, a single power supply set of voltages (Vdd, Gnd) is accordingly used for the cell supply, WL high voltage and BLT/BLF high voltage. In stand-by mode, WL=Gnd, BLT/BLF=Vdd. In read mode, the WL transitions to Vdd, and BLT/BLF are left floating. In an exemplary read operation, the transfer (passgate) transistors M5 and M6 are simultaneously actuated through the wordline WL and a current flows from the bitline to ground through transistors M1 and M5. A rise in voltage is observed at the true data storage node Q having a value which depends on the strength of the transistors M1 and M5. An excess rise in the voltage at the true data storage node Q can turn transistor M3 on causing cell data to be flipped to the opposite value. This condition is referred to in the art as read instability.
Local mismatch plays an important role in cell stability. Furthermore, it is known to those skilled in the art that the effect of mismatch increases as the supply voltage Vdd is lowered. Each cell design is qualified down to a lowest supply voltage Vdd(min) at which the cell stability meets a qualification target. The value of Vdd(min) accordingly acts as a restriction on low voltage functionality of the memory cell when used alone or when integrated with other components and circuits.
There is a need in the art to provide a memory cell suitable for stable operation in integrated circuit configurations that utilize low supply voltage levels.